Analog-to-digital converter (ADC) with background calibration

An analog-to-digital converter (ADC) with a background calibration process is disclosed. In one aspect, an ADC has a plurality of comparators that each compare an input voltage to a voltage generated at a tap across a plurality of references (e.g., reference resistor ladders). The comparators are initially calibrated with a foreground calibration routine, and recalibration continues to compensate for aging, voltage and temperature variations by randomly offline one of the plurality of comparators to run a calibration process without replacing the comparator, without interrupting operation of the ADC. The values of the offline comparators may be reliably inferred from values from neighboring comparators, or randomly guessed in some cases. Although possible errors may be introduced, such errors may be driven to a quantized-mean-square noise level by exemplary aspects of the present disclosure. 公开了具有后台校准过程的模/数转换器(ADC)。在一个方面，一种具有多个比较器的ADC，所述多个比较器各自将输入电压与在跨多个参考(例如，参考电阻器梯)的分接头处生成的电压进行比较。所述比较器最初用前台校准例程进行校准，并且通过随机使所述