Memory, access method and electronic equipment

The invention discloses a memory, an access method and electronic equipment, and relates to the technical field of semiconductors. The memory comprises a plurality of memory cell layers which are stacked along a direction vertical to a substrate, and a plurality of word lines and a plurality of bit lines which are correspondingly connected with memory cells in the memory cell layers, wherein the word lines extend along a first direction parallel to the substrate, and one word line is connected with one row of storage units in the storage unit layer; the bit lines extend along the direction vertical to the substrate, and one bit line is connected with one column of memory cells arranged along the direction vertical to the substrate in different memory cell layers; and the word line selection circuit is respectively connected with the word lines extending along the first direction parallel to the substrate, and is configured to provide a layer selection signal and a row gating signal in response to an access re