Silicon carbide wafer and silicon carbide semiconductor device using same
The invention provides a silicon carbide wafer and a silicon carbide semiconductor device using the same. This silicon carbide wafer is provided with a substrate (10) comprising SiC, and an epitaxial layer (20) comprising SiC and disposed on the substrate, and has a chip formation region in which a...
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creator | UEHIGASHI HIDEYUKI |
description | The invention provides a silicon carbide wafer and a silicon carbide semiconductor device using the same. This silicon carbide wafer is provided with a substrate (10) comprising SiC, and an epitaxial layer (20) comprising SiC and disposed on the substrate, and has a chip formation region in which a semiconductor element is formed, and an outer peripheral region surrounding the chip formation region. The epitaxial layer has a trap density of 1.0 * 1013 cm or less at an activation energy of 0.10-0.20 eV derived by a DLTS method in the chip formation region, and the substrate has a Ti density and a Cr density of 1.0 * 1017 cm or less as measured by an SIMS method.
一种碳化硅晶片以及使用了该碳化硅晶片的碳化硅半导体装置。碳化硅晶片具备由SiC构成的基板(10)、以及由SiC构成并配置于基板上的外延层(20),并具有形成半导体元件的芯片形成区域、以及包围芯片形成区域的外周区域。外延层在芯片形成区域中通过DLTS法导出的0.10~0.20eV的活化能中的陷阱密度设为1.0×1013cm-3以下,基板通过SIMS法测定的Ti密度以及Cr密度分别设为1.0×1017cm-3以下。 |
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一种碳化硅晶片以及使用了该碳化硅晶片的碳化硅半导体装置。碳化硅晶片具备由SiC构成的基板(10)、以及由SiC构成并配置于基板上的外延层(20),并具有形成半导体元件的芯片形成区域、以及包围芯片形成区域的外周区域。外延层在芯片形成区域中通过DLTS法导出的0.10~0.20eV的活化能中的陷阱密度设为1.0×1013cm-3以下,基板通过SIMS法测定的Ti密度以及Cr密度分别设为1.0×1017cm-3以下。</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240628&DB=EPODOC&CC=CN&NR=118263285A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240628&DB=EPODOC&CC=CN&NR=118263285A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>UEHIGASHI HIDEYUKI</creatorcontrib><title>Silicon carbide wafer and silicon carbide semiconductor device using same</title><description>The invention provides a silicon carbide wafer and a silicon carbide semiconductor device using the same. This silicon carbide wafer is provided with a substrate (10) comprising SiC, and an epitaxial layer (20) comprising SiC and disposed on the substrate, and has a chip formation region in which a semiconductor element is formed, and an outer peripheral region surrounding the chip formation region. The epitaxial layer has a trap density of 1.0 * 1013 cm <-3 > or less at an activation energy of 0.10-0.20 eV derived by a DLTS method in the chip formation region, and the substrate has a Ti density and a Cr density of 1.0 * 1017 cm <-3 > or less as measured by an SIMS method.
一种碳化硅晶片以及使用了该碳化硅晶片的碳化硅半导体装置。碳化硅晶片具备由SiC构成的基板(10)、以及由SiC构成并配置于基板上的外延层(20),并具有形成半导体元件的芯片形成区域、以及包围芯片形成区域的外周区域。外延层在芯片形成区域中通过DLTS法导出的0.10~0.20eV的活化能中的陷阱密度设为1.0×1013cm-3以下,基板通过SIMS法测定的Ti密度以及Cr密度分别设为1.0×1017cm-3以下。</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAMzszJTM7PU0hOLErKTElVKE9MSy1SSMxLUShGkylOzQXxU0qTS_KLFFJSyzKTUxVKizPz0hWKE3NTeRhY0xJzilN5oTQ3g6Kba4izh25qQX58anFBYnJqXmpJvLOfoaGFkZmxkYWpozExagDcBTSx</recordid><startdate>20240628</startdate><enddate>20240628</enddate><creator>UEHIGASHI HIDEYUKI</creator><scope>EVB</scope></search><sort><creationdate>20240628</creationdate><title>Silicon carbide wafer and silicon carbide semiconductor device using same</title><author>UEHIGASHI HIDEYUKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118263285A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>UEHIGASHI HIDEYUKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>UEHIGASHI HIDEYUKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Silicon carbide wafer and silicon carbide semiconductor device using same</title><date>2024-06-28</date><risdate>2024</risdate><abstract>The invention provides a silicon carbide wafer and a silicon carbide semiconductor device using the same. This silicon carbide wafer is provided with a substrate (10) comprising SiC, and an epitaxial layer (20) comprising SiC and disposed on the substrate, and has a chip formation region in which a semiconductor element is formed, and an outer peripheral region surrounding the chip formation region. The epitaxial layer has a trap density of 1.0 * 1013 cm <-3 > or less at an activation energy of 0.10-0.20 eV derived by a DLTS method in the chip formation region, and the substrate has a Ti density and a Cr density of 1.0 * 1017 cm <-3 > or less as measured by an SIMS method.
一种碳化硅晶片以及使用了该碳化硅晶片的碳化硅半导体装置。碳化硅晶片具备由SiC构成的基板(10)、以及由SiC构成并配置于基板上的外延层(20),并具有形成半导体元件的芯片形成区域、以及包围芯片形成区域的外周区域。外延层在芯片形成区域中通过DLTS法导出的0.10~0.20eV的活化能中的陷阱密度设为1.0×1013cm-3以下,基板通过SIMS法测定的Ti密度以及Cr密度分别设为1.0×1017cm-3以下。</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Silicon carbide wafer and silicon carbide semiconductor device using same |
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