Method for reducing side wall loss in groove etching process

The invention provides a method for reducing side wall loss in a groove etching process, which comprises the following steps of: providing a semiconductor structure which comprises a substrate, STI (Shallow Trench Isolation) formed in the substrate, an active region defined by the STI, a germanium-silicon epitaxial layer formed in the active region, a plurality of gate laminated structures formed on the surface of the germanium-silicon epitaxial layer, and source and drain regions corresponding to the gate laminated structures; forming a first side wall layer and a second side wall layer on the surface of the semiconductor structure; an etching barrier layer is formed on the surfaces of the source region, the drain region and the STI, the etching barrier layer is formed on the surface of the second side wall layer, and the thickness of the etching barrier layer is smaller than that of the gate laminated structure; forming a protection layer on the surface of the second side wall layer which is positioned abov