Three-dimensional (3D) memory device and method of manufacture
A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening exposing the sacrificial layer, removing the sacrificial layer to create a cavity and e...
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| creator | LI SHAN HUO ZONGLIANG LIU XIAOXIN YUAN WEI GAO TINGTING SONG ZHIHAO XIA ZHILIANG YANG YI DU XIAOLONG SUN CHANGZHI |
| description | A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening exposing the sacrificial layer, removing the sacrificial layer to create a cavity and expose a portion of the channel hole structure, forming a semiconductor layer to fill the cavity, and forming a second dielectric stack over the semiconductor layer. The opening is filled with a fill structure, and a second dielectric stack is formed over the fill structure. The opening is made of a gate gap (GLS) structure.
公开了一种用于制造3D存储装置的方法，包括：在衬底之上形成牺牲层，在牺牲层之上形成第一电介质堆叠体，形成沟道孔结构，形成暴露牺牲层的开口，去除牺牲层以产生空腔并暴露沟道孔结构的一部分，形成半导体层以填充空腔，用填充结构填充开口，并在填充结构之上形成第二电介质堆叠体。所述开口是为栅缝隙(GLS)结构制作的。 |
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公开了一种用于制造3D存储装置的方法，包括：在衬底之上形成牺牲层，在牺牲层之上形成第一电介质堆叠体，形成沟道孔结构，形成暴露牺牲层的开口，去除牺牲层以产生空腔并暴露沟道孔结构的一部分，形成半导体层以填充空腔，用填充结构填充开口，并在填充结构之上形成第二电介质堆叠体。所述开口是为栅缝隙(GLS)结构制作的。</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240621&DB=EPODOC&CC=CN&NR=118234236A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240621&DB=EPODOC&CC=CN&NR=118234236A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LI SHAN</creatorcontrib><creatorcontrib>HUO ZONGLIANG</creatorcontrib><creatorcontrib>LIU XIAOXIN</creatorcontrib><creatorcontrib>YUAN WEI</creatorcontrib><creatorcontrib>GAO TINGTING</creatorcontrib><creatorcontrib>SONG ZHIHAO</creatorcontrib><creatorcontrib>XIA ZHILIANG</creatorcontrib><creatorcontrib>YANG YI</creatorcontrib><creatorcontrib>DU XIAOLONG</creatorcontrib><creatorcontrib>SUN CHANGZHI</creatorcontrib><title>Three-dimensional (3D) memory device and method of manufacture</title><description>A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening exposing the sacrificial layer, removing the sacrificial layer to create a cavity and expose a portion of the channel hole structure, forming a semiconductor layer to fill the cavity, and forming a second dielectric stack over the semiconductor layer. The opening is filled with a fill structure, and a second dielectric stack is formed over the fill structure. The opening is made of a gate gap (GLS) structure.
公开了一种用于制造3D存储装置的方法，包括：在衬底之上形成牺牲层，在牺牲层之上形成第一电介质堆叠体，形成沟道孔结构，形成暴露牺牲层的开口，去除牺牲层以产生空腔并暴露沟道孔结构的一部分，形成半导体层以填充空腔，用填充结构填充开口，并在填充结构之上形成第二电介质堆叠体。所述开口是为栅缝隙(GLS)结构制作的。</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLALyShKTdVNycxNzSvOzM9LzFHQMHbRVMhNzc0vqlRISS3LTE5VSMxLAYqUZOSnKOSnKeQm5pWmJSaXlBal8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41OKCxOTUvNSSeGc_Q0MLI2MTI2MzR2Ni1AAA6S8vrg</recordid><startdate>20240621</startdate><enddate>20240621</enddate><creator>LI SHAN</creator><creator>HUO ZONGLIANG</creator><creator>LIU XIAOXIN</creator><creator>YUAN WEI</creator><creator>GAO TINGTING</creator><creator>SONG ZHIHAO</creator><creator>XIA ZHILIANG</creator><creator>YANG YI</creator><creator>DU XIAOLONG</creator><creator>SUN CHANGZHI</creator><scope>EVB</scope></search><sort><creationdate>20240621</creationdate><title>Three-dimensional (3D) memory device and method of manufacture</title><author>LI SHAN ; HUO ZONGLIANG ; LIU XIAOXIN ; YUAN WEI ; GAO TINGTING ; SONG ZHIHAO ; XIA ZHILIANG ; YANG YI ; DU XIAOLONG ; SUN CHANGZHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN118234236A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>LI SHAN</creatorcontrib><creatorcontrib>HUO ZONGLIANG</creatorcontrib><creatorcontrib>LIU XIAOXIN</creatorcontrib><creatorcontrib>YUAN WEI</creatorcontrib><creatorcontrib>GAO TINGTING</creatorcontrib><creatorcontrib>SONG ZHIHAO</creatorcontrib><creatorcontrib>XIA ZHILIANG</creatorcontrib><creatorcontrib>YANG YI</creatorcontrib><creatorcontrib>DU XIAOLONG</creatorcontrib><creatorcontrib>SUN CHANGZHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LI SHAN</au><au>HUO ZONGLIANG</au><au>LIU XIAOXIN</au><au>YUAN WEI</au><au>GAO TINGTING</au><au>SONG ZHIHAO</au><au>XIA ZHILIANG</au><au>YANG YI</au><au>DU XIAOLONG</au><au>SUN CHANGZHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Three-dimensional (3D) memory device and method of manufacture</title><date>2024-06-21</date><risdate>2024</risdate><abstract>A method for fabricating a 3D memory device includes forming a sacrificial layer over a substrate, forming a first dielectric stack over the sacrificial layer, forming a channel hole structure, forming an opening exposing the sacrificial layer, removing the sacrificial layer to create a cavity and expose a portion of the channel hole structure, forming a semiconductor layer to fill the cavity, and forming a second dielectric stack over the semiconductor layer. The opening is filled with a fill structure, and a second dielectric stack is formed over the fill structure. The opening is made of a gate gap (GLS) structure.
公开了一种用于制造3D存储装置的方法，包括：在衬底之上形成牺牲层，在牺牲层之上形成第一电介质堆叠体，形成沟道孔结构，形成暴露牺牲层的开口，去除牺牲层以产生空腔并暴露沟道孔结构的一部分，形成半导体层以填充空腔，用填充结构填充开口，并在填充结构之上形成第二电介质堆叠体。所述开口是为栅缝隙(GLS)结构制作的。</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | ELECTRICITY |
| title | Three-dimensional (3D) memory device and method of manufacture |
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