Semiconductor device and forming method thereof

A semiconductor device includes a backside gate etch stop layer (ESL) on a backside of a first gate stack, where a plurality of first nanostructures overlap the backside gate ESL. The backside gate ESL may include a high-k dielectric material. The semiconductor device also includes a plurality of first nanostructures extending between the first source/drain regions and a plurality of second nanostructures extending over the plurality of first nanostructures and between the second source/drain regions. A first gate stack is disposed around the plurality of first nanostructures, and a second gate stack over the first gate stack is disposed around the plurality of second nanostructures. A backside gate contact extends through the backside gate ESL to electrically couple to the first gate stack. The embodiment of the invention also discloses a method for forming the semiconductor device. 一种半导体器件，包括在第一栅极堆叠件的背侧上的背侧栅极蚀刻停止层(ESL)，其中多个第一纳米结构与背侧栅极ESL重叠。背侧栅极ESL可以包括高k介电材料。半导体器件还包括在第一源极/漏极区之间延伸的多个第一纳米结构和在多个第一纳米结构上方并在第二源极/漏