Refresh control circuit, data refresh circuit, data refresh method and storage device
The invention provides a refresh control circuit, a data refresh circuit, a data refresh method and a storage device, and the circuit comprises a weak bit refresh control signal generation circuit which is used for receiving a refresh command signal and a row hammer refresh control signal to generat...
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| Hauptverfasser: | , , |
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| Format: | Patent |
| Sprache: | chi ; eng |
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| Online-Zugang: | Volltext bestellen |
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| Zusammenfassung: | The invention provides a refresh control circuit, a data refresh circuit, a data refresh method and a storage device, and the circuit comprises a weak bit refresh control signal generation circuit which is used for receiving a refresh command signal and a row hammer refresh control signal to generate a weak bit refresh control signal; the control input end of the address control circuit is used for respectively receiving a weak bit refresh control signal and a row hammering refresh control signal, and the data input end of the address control circuit is used for respectively receiving a weak bit row address, a row hammering refresh address and a normal row address in the storage circuit; and generating a to-be-refreshed row address according to the weak bit row address, the row hammering refresh address or the normal row address under the control of the weak bit refresh control signal and the row hammering refresh control signal, and the weak bit row address comprises the row address where the storage unit of |
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