Memory management unit and method of traversing multi-level page table
A memory management unit and a method of traversing a multi-level page table are provided. The memory management unit includes a TLB configured to cache a PTE including a mapping relationship between a virtual frame number and a physical frame number, and to convert a virtual address into a physical...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | A memory management unit and a method of traversing a multi-level page table are provided. The memory management unit includes a TLB configured to cache a PTE including a mapping relationship between a virtual frame number and a physical frame number, and to convert a virtual address into a physical address using the cached PTE. The page table traversal request queue is configured to queue a page table traversal request corresponding to a virtual page number when a TLB miss occurs, and the one or more PTWs are configured to retrieve a PTE from a main memory and convert the virtual page number to a physical frame number using the PTE. The PTW is configured to select an associated page table traversal request having the same base address corresponding to a virtual page number, continuously provide cache line requests for obtaining PTE corresponding to the associated page table traversal request, obtain PTE corresponding to the associated PTE request, and provide the obtained PTE to the TLB.
提供了存储器管理单元和遍历多级页表的方法 |
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