MEMORY DEVICE AND OPERATING METHOD THEREOF

A memory device includes memory cells respectively connected with word lines; a first ground selection transistor connected to the first ground selection line and programmed to have a first threshold voltage; a second ground selection transistor connected to the second ground selection line and prog...

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Bibliographische Detailangaben
Hauptverfasser: CHOI YONG-HYUK, KIM SEUNG-BUM
Format: Patent
Sprache:chi ; eng
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Beschreibung
Zusammenfassung:A memory device includes memory cells respectively connected with word lines; a first ground selection transistor connected to the first ground selection line and programmed to have a first threshold voltage; a second ground selection transistor connected to the second ground selection line and programmed to have a second threshold voltage different from the first threshold voltage; and a control circuit configured to: control to perform an erase operation on each of at least one first ground selection transistor of the first ground selection transistors based on a threshold voltage of each of the at least one first ground selection transistor being greater than a predetermined first criterion; and controlling a threshold voltage of each of the second ground selection transistors to be compared with a predetermined second criterion based on completion of the erase operation of the at least one first ground selection transistor. 一种存储器件包括:分别地与字线连接的存储器单元;与第一接地选择线连接的、被编程为具有第一阈值电压的第一接地选择晶体管;与第二接地选择线连接的、被编程为具有不同于第一