SPI (Serial Peripheral Interface) isolation chip digital signal time sequence control method and SPI isolation chip

The embodiment of the invention provides an SPI (Serial Peripheral Interface) isolation chip digital signal time sequence control method and an SPI isolation chip. The SPI isolation chip digital signal time sequence control method comprises the following steps: judging whether an input first digital signal and an input second digital signal are effective or not; and comparing the mutual sampling results of the first digital signal and the second digital signal to determine whether the received differential signal has the preset logic level so as to determine the effectiveness of the received differential signal, so that stable and reliable data transmission can be realized, the cost is low, and the probability of error locking of a transmission path is greatly reduced. The use of phase-locked loops and high-frequency synchronous clock data recovery circuits can be greatly reduced from the circuit structure, and the control logic is simplified, so that the circuit area is reduced, and the cost is reduced. 本申请实