MEMORY CONTROL DEVICE AND OPERATING METHOD THEREOF

The invention provides a memory control device and a memory control device operation method. The memory control apparatus includes an instruction memory block, a plurality of physical memory blocks, a processing circuit, a decoder, and a controller. The instruction memory block stores a plurality of instructions. The plurality of physical memory blocks respectively store one of a plurality of load instructions in the plurality of instructions. The processing circuitry provides an instruction address. The decoder receives an instruction address. The decoder provides a control signal when the instruction address is not equal to a plurality of memory addresses of a plurality of load instructions stored in the instruction memory block. The controller responds to the control signal to determine a target entity memory block corresponding to the load instruction with the lowest number of uses, and stores a target instruction corresponding to the instruction address in the plurality of instructions to the target enti