Digital phase locked loop for frequency synthesis and associated merge duty cycle calibration scheme

A digital phase-locked loop for frequency synthesis and a related merge duty cycle calibration scheme are provided. Techniques described herein relate to duty cycle error calibration. An example apparatus includes a multimode frequency divider (MMD) circuit configured to receive a first digital code...

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Bibliographische Detailangaben

Hauptverfasser:	ALI TAMER MOHAMMED, AL-MAHA AHMED SAWAT MOHAMMED ABOLANI, ABDULHADEF, MOHAMED, MOHSEN, ABDULLAH
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY
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