Digital phase locked loop for frequency synthesis and associated merge duty cycle calibration scheme

A digital phase-locked loop for frequency synthesis and a related merge duty cycle calibration scheme are provided. Techniques described herein relate to duty cycle error calibration. An example apparatus includes a multimode frequency divider (MMD) circuit configured to receive a first digital code corresponding to a first time delay and included in a first plurality of digital codes associated with a first time delay range, divide a clock signal by a divisor to generate a divided clock signal, and delay the divided clock signal by the first time delay, to generate a delayed clock signal. The apparatus may further include a digitally controlled delay line (DCDL) circuit configured to receive a second digital code corresponding to a second time delay and included in a second plurality of digital codes associated with a second time delay range, and delay the delayed clock signal by the second time delay to generate a feedback clock signal, to reduce a difference between the feedback clock signal and the refere