Small-size low-power-consumption T trigger

The invention belongs to the field of integrated circuits, and particularly relates to a small-size low-power-consumption T flip-flop which comprises three NMOS (N-channel metal oxide semiconductor) tubes, two PMOS (P-channel metal oxide semiconductor) tubes, three phase inverters and a capacitor C. INV1 and INV2 in the three phase inverters form a latch, and INV3 is an output buffer. The time sequence logic, data loading and data reading functions of the T flip-flop are realized by controlling the turn-off and turn-on of the three NMOS transistors and the two PMOS transistors, the T flip-flop has the advantages of low power consumption, simple circuit structure and the like, and the reasonable optimization of the overall circuit area performance and the improvement of the integration level are realized on the circuit layout. 本发明属于集成电路领域，具体为一种小尺寸低功耗的T触发器，该触发器包括3个NMOS管、2个PMOS管、3个反相器以及1个电容C，3个反相器中INV1和INV2构成锁存器，INV3为输出缓存器。通过控制3个NMOS管和2个PMOS管的关断和导通，实现T触发器的时序逻辑、数据载入和数据读取功能，具有低功耗、电路结构简单等优点，且在电路布局上实现了整体电路面积性能的合理优化和