Method for manufacturing anti-SEB power VDMOS

The invention discloses an anti-SEB power VDMOS manufacturing method, and belongs to the technical field of VDMOS devices. Providing a silicon wafer, and performing JFET injection; carrying out Pbody photoetching and Pbody injection, and carrying out Pbody knot pushing; performing n-photoetching and n-injection on the surface of the silicon wafer, and sequentially forming gate oxide and a polycrystal grid electrode; lPCVD is carried out to deposit SiO2, spacer corrosion is carried out to form a side wall, and then n + photoetching, n + injection, PSEB injection, p + photoetching and p + injection are carried out; pMD deposition and contact hole etching are carried out; and front metal Al and back metal TiNiAg are formed. The method can be used for designing and manufacturing power devices in an electric propulsion system and a power supply system in the aerospace field, and efficient power electronic conversion is achieved in a radiation environment. 本发明公开一种抗SEB功率VDMOS制造方法，属于VDMOS器件技术领域。提供硅晶圆，进行JFET注入；进行Pbody