Integrated circuit structure and manufacturing method thereof

The invention provides an integrated circuit structure and a manufacturing method thereof. The integrated circuit structure includes a substrate, a plurality of semiconductor elements, an interlayer dielectric structure, an internal connection structure, a dielectric layer, a conductive layer, an etch stop layer, and a plurality of memory cells. The semiconductor element is located on the substrate. The interlayer dielectric structure is over the semiconductor device. The internal connection structure is located in the interlayer dielectric structure and is electrically connected to the semiconductor element. The dielectric layer is over the interlayer dielectric structure. The etching barrier layer is located on the dielectric layer. The conductive layer is located on the etch stop layer. The memory cells are stacked over the etch stop layer in a vertical direction. 本公开提供一种集成电路结构及其制造方法，该集成电路结构包括衬底、多个半导体元件、层间介电结构、内连接结构、介电层、导电层、刻蚀阻挡层以及多个存储器单元。半导体元件位于衬底上。层间介电结构位于半导体元件上方。内连接结构位于层间介电结构中，且电性连接于半导体元件。介电层位于层间介电结构上方。