Memory device including page buffer circuit

A memory device including a page buffer circuit is provided. The memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including a plurality of page buffer units connected to the plurality of memory cells through a plurality of bit lines, respectively. A sense node is connected to a bit line of each buffer circuit. The plurality of page buffer units are respectively connected with the sensing nodes, and each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wirings near the sense node are used to reduce coupling issues caused by low capacitance of the sense node. 提供包括页缓冲器电路的存储器装置。所述存储器装置包括：存储器单元阵列，包括多个存储器单元；以及页缓冲器电路，包括多个页缓冲器单元，所述多个页缓冲器单元通过多条位线分别与所述多个存储器单元连接。感测节点连接到每个缓冲器电路的位线。所述多个页缓冲器单元分别与感测节点连接，所述多个页缓冲器单元中的每个包括至少一个晶体管。感测节点附近的一条或多条辅助布线用于减少由感测节点的低电容导致的耦合问题。