STACKED DEVICE STRUCTURE AND METHOD OF FORMING THE SAME AND METHOD OF FORMING TRANSISTOR

Disclosed herein are dipole engineering techniques for devices of stacked device structures. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes forming a high-k dielectric layer; forming an n-dipole dopant source layer over the high-k dielectric layer; performing a thermal drive-in process, wherein the thermal drive-in process drives the n-dipole dopant from the n-dipole dopant source layer into the high-k dielectric layer; and forming at least one conductive gate layer over the high-k dielectric layer after removing the n-dipole dopant source layer. The thermal drive-in process has a drive-in temperature of less than 600 DEG C (e.g., about 300 DEG C to about 500 DEG C). The n-dipole dopant is strontium, erbium, magnesium, or a combination thereof. The method may also include adjusting thermal drive-in process parameters to provide a gate dielectric having an n-dipole dopant profile, the p-dipole dopant profile having a peak at a high k/surface