Cyclic redundancy check method and chip

The embodiment of the invention provides a cyclic redundancy check method and a chip, and the method comprises the steps: setting a value of a state control register, the value of the state control register being used for representing whether the check needs to carry out the reverse sequence on the checked bytes included in the input data or not; respectively executing the following operations on the ith checked byte of the input data to obtain a checking result: loading multi-bit input data corresponding to the ith checked byte; according to a verification instruction, verification operation is carried out on the ith verified byte, an ith verification result is obtained, the verified byte is stored in a second operand register corresponding to the verification instruction, and the ith verification result is obtained; the check instruction performs bit logic operation on a number stored in the second operand register and a number stored in the first operand register through a loop mode, and the first operand