SRAM structure with adjustable operation speed and manufacturing method thereof

The invention provides an SRAM (Static Random Access Memory) structure with an adjustable operation speed. The SRAM structure comprises four PMOS (P-channel Metal Oxide Semiconductor) transistors PG1, PG2, PU1 and PU2 and four NMOS (N-channel Metal Oxide Semiconductor) transistors PD1, PD2, RP PD and RP PG, wherein the PD1, the PD2 and the RP PD are pull-down tubes, the PU1 and the PU2 are ascending tubes, the PG1 and the PG2 are transmission tubes, and the RP PG is a gate tube; wherein the PG1, the PG2, the PU1, the PU2, the PD1 and the PD2 form a six-transistor SRAM (Static Random Access Memory) structure, and the six-transistor SRAM structure is controlled by signals A-WL, BL1 and BL2; the RP PD and the RP PG serve as reading ports and are controlled by signals B-WL and RP BL; the gate structures of the PU1 and the PU2 are configured for a first target work function; the gate structures of the PG1, the PG2, the PD1 and the PD2 are configured for a second target work function; and the grid structures of the