Ferroelectric memory device and method of fabricating same

A memory device includes a plurality of memory cells and a wiring interconnect structure in electrical contact with the memory cells. Each memory cell includes at least one first transistor, a cell interconnect structure, and at least one capacitor. The cell interconnect structure is formed over and in electrical contact with the at least one first transistor, and includes a cell plate disposed at a top layer of the cell interconnect structure. The capacitor is electrically coupled to the at least one first transistor through the cell interconnect structure. Each capacitor includes a first electrode, a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode. The wiring interconnection structure includes a first conductive layer and a first via structure disposed on the first conductive layer. The first via structure is in electrical contact with the first electrode through the second conductive layer. The first conductive layer is under the second conductive l