Integrated circuit

An integrated circuit comprises a power-on reset circuit, a watchdog timer, an AND gate and a power management control circuit. The power-on reset circuit is used for receiving an input voltage to generate a power-on reset signal and generating a clock signal. The watchdog timer is used for generating an expiration signal according to a clock signal when the power-on reset signal has the enabling voltage, and the clock signal enables the expiration signal to have an expiration pulse every preset time. The AND gate comprises a first input end, is coupled to the power-on reset circuit and is used for receiving a power-on reset signal; the second input end is coupled to the watchdog timer and is used for receiving the expiration signal; and the output end is used for outputting a reset signal according to the power-on reset signal and the expiration signal. The power management control circuit is coupled to the AND gate for resetting the output current in response to a reset pulse on the reset signal. 一种集成电路，包含开