Time-sensitive network asynchronous traffic scheduling method and system based on FPGA
The invention provides a time-sensitive network asynchronous traffic scheduling method and system based on an FPGA, and the method comprises the following steps: receiving a data frame, buffering the data frame to an FIFO buffer module, reading the data frame in the FIFO buffer module through a stre...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention provides a time-sensitive network asynchronous traffic scheduling method and system based on an FPGA, and the method comprises the following steps: receiving a data frame, buffering the data frame to an FIFO buffer module, reading the data frame in the FIFO buffer module through a stream filter module, adding packaging information, outputting the data frame to a service data unit filter module, and outputting the data frame to a service data unit filter module; the data frames are transmitted to the ATS algorithm scheduling module through the corresponding flow gating module according to the packaging information, the data frame compliance time point is calculated through the ATS algorithm scheduling module, the data frames are written into the shared queue according to the priority information, the legality of the data frames is judged according to the data frame compliance time point, and the data frames are output. According to the time-sensitive network asynchronous traffic scheduling method |
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