Extremely low voltage I/O circuit and defect screening method

The invention relates to a very low voltage I/O circuit and a defect screening method. A GPIO includes: a transmitter having an output stage connected to an I/O pad and adapted to supply transmission data to the I/O pad for a transmission operation in response to output data generated by low-voltage core logic operating within a functional voltage range; a receiver suitable for supplying receive data to the low voltage core logic operating within the functional voltage range for a receive operation in response to input data received at the I/O pad; a VLV transmitter adapted to supply VLV transmit data to the output stage of the transmitter, rather than directly to the I/O pad, in response to output test data generated by the low voltage core logic; and a VLV receiver adapted to supply VLV receive data to the low voltage core logic operating within a low core power supply voltage range in response to input data received from the output stage of the transmitter. 本公开涉及极低电压I/O电路和缺陷筛选方法。一种GPIO包括：发送器，具有连接到I/O垫的输出级并