SEMICONDUCTOR DIE MODULE PACKAGES HAVING VAPOR DEFINING SEGMENTS IN METAL STRUCTURES IN A PACKAGE SUBSTRATE TO REDUCE DIE-SUBSTRATE

Semiconductor die module packages having void-defining sections in a metal structure in a package substrate to reduce die-substrate mechanical stresses and related methods of manufacture. To reduce die-substrate mechanical stresses between the package substrate and a die of the die module package, v...

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Bibliographische Detailangaben
Hauptverfasser: DETLEFSEN ANDREAS, BILLON JEROME
Format: Patent
Sprache:chi ; eng
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Zusammenfassung:Semiconductor die module packages having void-defining sections in a metal structure in a package substrate to reduce die-substrate mechanical stresses and related methods of manufacture. To reduce die-substrate mechanical stresses between the package substrate and a die of the die module package, void-defining segments are formed in a metal structure in a metallization layer of the package substrate. The void-defining section is formed by one or more cutouts in a defined area of a metal material of the metal structure to reduce stiffness, which also has the effect of reducing the effective coefficient of thermal expansion (CTE) of the package substrate. The metal material remaining between the metal cuts in the void-defining sections forms a metal interconnect. A die interconnect may directly couple a die to the metal interconnect in the void-defined section in the metal structure to reduce mechanical stresses between the die and the die interconnect to the package substrate. 在封装衬底中的金属结构中具有空隙限定区段以减小管芯-衬底机械应力