Fault positioning circuit and method, chip and computer readable storage medium
The invention discloses a fault positioning circuit and method, a chip and a computer readable storage medium, and belongs to the technical field of integrated circuit testing. The fault positioning circuit is provided with a special debugging chain, the structure is simple, and a scanning chain wit...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention discloses a fault positioning circuit and method, a chip and a computer readable storage medium, and belongs to the technical field of integrated circuit testing. The fault positioning circuit is provided with a special debugging chain, the structure is simple, and a scanning chain with a fault can be identified by using a conventional scanning chain diagnosis method, namely, the column coordinate of a fault scanning unit is obtained; then shifting and inputting a specific test vector, and through the XOR processing output by the scanning unit at the same level, capturing the numerical value by the scanning unit corresponding to the special debugging chain, thereby obtaining the row coordinate of the fault scanning unit, effectively solving the problem of pollution to subsequent data caused by the fault scanning unit when shifting data encounters the fault scanning unit, and improving the working efficiency. And finally, high-precision positioning of the fault scanning unit is realized.
本申请公开了一种 |
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