Router and routing method for multi-core network-on-chip

The invention belongs to the technical field of network-on-chip routing, and particularly relates to a router and a routing method for a multi-core network-on-chip. The system comprises a data caching module, an adjacent matrix module and a clock gating module, the data caching module is composed of N FIFO memories which are respectively connected with the N source cores, the input of the adjacent matrix module is connected with the output of the data caching module, the output of the adjacent matrix module is connected with the N target cores, and the adjacent matrix module is used for selecting connection paths between the data caching module and the target cores; an input signal of the clock gating module is an input clock and gating enable, and whether the router works or not is controlled through the gating enable. According to the invention, the control logic is simple, the memory occupied by parameters is small, and the area overhead is smaller; a low-power-consumption design is adopted, so that the po