Heterogeneous chip architecture and scheduling method for realizing distributed automatic control instantaneity

The invention relates to the field of architecture and scheduling of heterogeneous chips, in particular to a heterogeneous chip architecture and scheduling method for realizing distributed automatic control instantaneity, and the heterogeneous chip architecture comprises an MCU (Microprogrammed Control Unit), a CPU (Central Processing Unit) and a switching chip; the CPU is used for realizing data acquisition, industrial operation and maintenance and man-machine interaction; the exchange chip is provided with an FPGA (Field Programmable Gate Array) architecture and is used for providing on-chip data exchange, computing power distribution and computing power scheduling; a computing power matrix is formed among the MCU, the CPU and the switching chip, and the MCU, the CPU and the switching chip communicate with one another through a communication bus; wherein common data exchange is carried out between the MCU and the CPU, bus scheduling in data exchange is managed by using an exchange chip, and a time sensitive