NONVOLATILE MEMORY DEVICE

A non-volatile memory device is provided that includes a page buffer circuit having a multi-level structure in which one level of the multi-level structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of the first to sixth bit lines and a second high voltage transistor connected to one of the seventh to twelfth bit lines, and the first low voltage region includes a first transistor connected to the first high voltage transistor. The second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage region has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines. 提供一种非易失性存储器件，该非易失性存储器件包括具有多级结构的页缓冲器电路，其中多级结构的一级包括高电压区、第一低电压区和第二低电压区。高电压区包括连接到第一至第六位线中的一条的第一高电压晶体管和连接到第七至第十二位线中的一条的第二高电压晶体管，第一低电压