Hardware accelerator and method for transfer operations

Methods and apparatus related to transfer operations are described. In one embodiment, a hardware processor comprises: a core to execute threads and transfer operations; and a first hardware accelerator and a second hardware accelerator for performing the operation, the first hardware accelerator and the second hardware accelerator are coupled to a plurality of shared buffers, an input buffer descriptor array of the second hardware accelerator having entries for each respective shared buffer, an input buffer response descriptor array of the second hardware accelerator having a corresponding response entry for each respective shared buffer, an output buffer descriptor array of the first hardware accelerator having an entry for each respective shared buffer, and an output buffer response descriptor array of the first hardware accelerator having a corresponding response entry for each respective shared buffer, the plurality of shared buffers to store output data from the first hardware accelerator and provide th