Method of forming high voltage transistors with thin gate polysilicon

The invention relates to a method of forming high voltage transistors with thin gate polysilicon. The invention discloses a semiconductor device and a manufacturing method thereof. The method includes depositing a polysilicon gate layer on a gate dielectric formed on a surface of a substrate in a peripheral region, forming a dielectric layer on the polysilicon gate layer, and depositing a height enhancement (HE) film on the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer, and the gate dielectric are then patterned to form a high voltage field effect transistor (HVFET) gate in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source region or a drain region in the substrate adjacent the HVFET gate. The HE film is then removed and a low voltage (LV) logic FET is formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal gate logic FET. 本申请涉及用薄栅极多晶硅形成高电压晶体管的方法。公开了一种半导体器件及其制造方法。该方法包括