Package substrate structure and manufacturing method thereof

The invention provides a package substrate structure and a manufacturing method thereof. The method includes forming a pad on a first carrier plate; pasting a conductive block on the exposed part of the first bearing plate; forming a substrate comprising a dielectric layer, a circuit layer, a first via hole and a second via hole on the first bearing plate; forming a connecting member including an insulating layer and a third via hole on the substrate; removing the conductive block and exposing the narrow end of the second via hole; and disposing a wafer on the second via. By means of the arrangement of the conductive blocks, the narrow ends of the second via holes are exposed subsequently, and the exposed narrow ends of the second via holes are connected with the wafer, so that the distance between the connecting ends is reduced. 本发明提供一种封装基板结构及其制造方法。方法包含形成接垫在第一承载板上；贴覆导电块在第一承载板的暴露部分上；形成包含介电层、线路层、第一导通孔及第二导通孔的基板在第一承载板上；形成包含绝缘层及第三导通孔的连接构件在基板上；移除导电块并暴露出第二导通孔的窄端；以及设置晶片在第二导通孔上。利用前述导电块的设置，而使后续暴露出第二导通孔的窄端，并利用暴露出第二导通孔的