Low-speed CPU inter-core even number last level compensation system and compensation method

The invention provides a low-speed CPU inter-core even number last level compensation system and compensation method. The system comprises a last even number judger, a last number flag register, a cache module and an even number decomposition module. The last even number judger comprises a last judger and an even number judger; the last bit judger is used for judging whether the serial data line data obtained when the sequential circuit is stopped is the last bit or not; the even number judger is used for judging whether the decimal number corresponding to the last preset number of binary numbers is an even number; the even number decomposition module is used for decomposing an even number into the sum of a preset number of odd prime numbers according to an even number decomposition table when the decimal number is judged to be the even number; the preset number of odd prime numbers are converted into corresponding preset number of binary numbers; the cache module is used for caching the binary numbers; and t