Memory queue operations for increasing throughput in ATE systems

The invention relates to memory queue operations for increasing throughput in ATE systems. A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs); and a hardware interface board operable to apply a test input signal to the plurality of DUTs and to receive a test output signal from the plurality of DUTs. The tester system further includes a memory including a plurality of buffers organized into a first-in first-out memory queue including a buffer front end and a buffer back end and receiving test mode data from the processor at the buffer front end; a direct memory access engine operable to read data from the buffer backend and to supply test mode data to the DUT; a buffer table for maintaining a buffer sequence within the plurality of buffers and vacancy and occupancy information about the plurality of buffers; and driver hardware operable to receive the test mode data and to drive the test input signal to the plurality of DUTs. 本公开