Method and device for checking time sequence of interface of to-be-tested design and electronic equipment

The invention discloses an interface time sequence checking method and device of a to-be-tested design and electronic equipment, and belongs to the field of computers. The method comprises the following steps: a time sequence generator in target equipment acquires a time sequence-free signal; the time sequence generator obtains a first target time sequence signal based on the non-time sequence signal; the first target time sequence signal is a signal with a time sequence; the time sequence generator inputs the first target time sequence signal into a to-be-tested design; a time sequence checker in the target equipment receives a second target time sequence signal output by the to-be-tested design; and the time sequence checker checks the second target time sequence signal to obtain a time sequence check result of the to-be-tested design. 本申请公开了一种待测设计的接口时序检查方法、装置和电子设备，属于计算机领域。该方法包括：目标设备中的时序生成器获取无时序信号；所述时序生成器基于所述无时序信号，获取第一目标时序信号；所述第一目标时序信号为有时序的信号；所述时序生成器将所述第一目标时序信号输入待测设计；目标设备中的时序检查器接收所述待测设计输出的第二目标时序信号；所述时序检查器对所