Memory with parallel main interface and test interface

The invention relates to a memory with parallel main and test interfaces. Memory dies may be configured with parallel interfaces that may individually (e.g., individually) support evaluation operations (e.g., before or as part of assembly) or access operations (e.g., after assembly into a multi-die...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	JOHNSON, JEFFREY, B, KEETH BRENT, NAKANO EIICHI, PAREKH KUNAL R, GRIFFIN AMY R
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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