Memory with parallel main interface and test interface

The invention relates to a memory with parallel main and test interfaces. Memory dies may be configured with parallel interfaces that may individually (e.g., individually) support evaluation operations (e.g., before or as part of assembly) or access operations (e.g., after assembly into a multi-die stack). For example, a memory die may include a first set of one or more contacts that support communication of signaling with or via another memory die in a multi-die stack. The memory die may also include a second set of one or more contacts that support detection of pre-assembly evaluation, the second set of one or more contacts may be electrically isolated from the first set of contacts. By implementing such a parallel interface, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve the ability to support a multi-die stack in a memory device. 本申请涉及具有并行主接口及测试接口的存储器。存储器裸片可经配置有可个别地(例如，单独地)支持评估操作(例如，在组装成多裸片堆叠之前或作为所述组装的部分)或存取操作(例如，在组装成多裸