Electrostatic discharge protection circuit and preparation method thereof

The present disclosure provides an electrostatic discharge (ESD) protection circuit. The protection circuit comprises an MOS transistor, a resistor and a capacitor. The MOS transistor is electrically coupled to a core circuit. The resistor is electrically coupled to a gate of the MOS transistor and generates a bias voltage on the gate to direct an ESD current to ground when an ESD event occurs on the core circuit. A layout of the MOS transistor is separated from a layout of the core circuit by a layout of a dummy structure. Techniques for fabricating the resistor include utilizing a portion of the dummy structure. The capacitor is connected between the resistor and a drain electrode of the MOS transistor. 本公开提供一种静电放电(ESD)保护电路。该保护电路包括一MOS晶体管、一电阻器及一电容器。该MOS晶体管电性耦接到一核心电路。该电阻器电性耦接到该MOS晶体管的一栅极而在该栅极上产生一偏压，以在该核心电路上发生一ESD事件时将一ESD电流导向一接地。该MOS晶体管的一布局借由一虚拟结构的一布局而与该核心电路的一布局分隔开。电阻器的制作技术包含利用该虚拟结构的一部分。电容器连接于该电阻器与MOS晶体管的一漏极之间。