Memory device including page buffer circuit

A memory device including a page buffer circuit includes: a memory cell array including a plurality of memory cells; the memory device includes a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units connected to the plurality of memory cells via a plurality of bit lines, respectively, and a plurality of cache latches corresponding to the plurality of page buffer units, respectively. The memory device includes a plurality of page buffer units each including a transfer transistor connected to a corresponding sensing node and driven according to a transfer control signal, and the memory device is configured such that: during a data sensing period, the transfer transistor is coupled to the plurality of page buffer units; the sensing node of a selected page buffer unit among the plurality of page buffer units is effectively connected to the sensing node of an unselected page buffer unit among the plurality of page buffer units. 一种包括页缓冲器电路的存储器件包括：存储单元阵列，所述存储单元阵列包括多个存储单元；以及