Logic gate circuit, latch and trigger

The invention provides a logic gate circuit, a latch and a trigger, relates to the field of logic circuits, and provides an NFET-based logic gate circuit. The logic gate circuit comprises a pull-up circuit, a pull-down circuit, a signal output end, at least one signal input end, a first voltage end and a second voltage end. The pull-up circuit includes a first NFET. Wherein the first NFET comprises a first grid electrode and a second grid electrode, a first pole of the first NFET and the first grid electrode are connected to a first voltage end, and a second pole of the first NFET and the second grid electrode are connected to a signal output end. The pull-down circuit comprises a second NFET; wherein the pull-down circuit is connected with the signal output end, the at least one signal input end and the second voltage end. The pull-down circuit is configured to control the second NFET according to the voltage of the at least one signal input end and pull down the voltage of the signal output end through the