DDR test system and method

The invention belongs to the technical field of DDR testing, and aims to provide a DDR testing system and method. According to the invention, the main control module generates the DDR test instruction in a coding mode, and when the DDR to be tested is tested, the instruction decoding control module decodes the DDR test instruction to obtain all sub test instructions in the DDR test instruction; and finally, all the sub-test instructions are converted into control signals conforming to a specified interface protocol through the DDR control module, and test operation is carried out on the tested DDR through the DDR physical layer. In the process, because the DDR test instruction is generated in a coding mode, compared with a scheme that a memory controller performs read-write test on the to-be-tested DDR directly based on a read-write operation instruction of a CPU in the traditional technology, accurate measurement of various time sequence parameters defined by DDR JEDEC can be realized, so that the to-be-test