Chip verification method, test case multiplexing method and device
The embodiment of the invention discloses a chip verification method and a test case reuse method and device.The chip verification method comprises the steps that configuration information of a verification model in a test case is read in a preset memory of a to-be-verified chip; the test case is ge...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The embodiment of the invention discloses a chip verification method and a test case reuse method and device.The chip verification method comprises the steps that configuration information of a verification model in a test case is read in a preset memory of a to-be-verified chip; the test case is generated based on a verification language different from a programming language supported by the to-be-verified core; the verification model corresponds to a virtual core adopted when the virtual chip is verified in a preset verification environment; and verifying the to-be-verified chip based on the configuration information.
本申请实施例公开了一种芯片验证方法、测试用例的复用方法及装置,其中,芯片验证方法包括:在待验证芯片的预设内存中,读取测试用例中验证模型的配置信息;测试用例基于与待验证核心所支持的编程语言不同的验证语言生成;验证模型对应于在预设验证环境中对虚拟芯片进行验证时采用的虚拟核心;基于配置信息,对待验证芯片进行验证。 |
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