Latch, flip-flop and chip

The invention provides a latch, a trigger and a chip, relates to the field of digital circuits, and can reduce the number of transistors in the trigger. The latch comprises a signal input end, a signal output end, a control signal end, a first voltage end, a second voltage end, a pull-up circuit and a pull-down circuit. Wherein the transistors in the latch all adopt N-type field effect transistors. The pull-up circuit is connected with the first voltage end and the signal output end. The pull-up circuit is configured to pull up the voltage of the signal output end according to the voltage of the first voltage end. The pull-down circuit is connected with the signal input end, the control signal end, the signal output end and the second voltage end. The pull-down circuit is configured to pull down the voltage of the signal output end according to the voltage of the second voltage end under the signal control of the control signal end and the signal input end. 本申请提供了一种锁存器、触发器及芯片，涉及数字电路领域，能够减少触发器中晶体管的数量。该锁存器包括信号输