Debugging method of high-flatness epitaxial wafer

The invention relates to a debugging method of a high-flatness epitaxial wafer, which belongs to the technical field of silicon wafer processing, and comprises the following operation steps: 1, the shape of a previous value is mostly in a bowl shape, that is, the edge upwarp has a depth, so that the ESFQR is poorer; 2, changing the power of a lamp tube in the epitaxial process, heating the silicon wafer from 750 DEG C to 900 DEG C, then heating to 1130 DEG C, and keeping the temperature for 45 seconds, so that a film of 2 microns grows on the silicon surface; and growing an epitaxial layer on the surface of the polished wafer through an epitaxial deposition reaction to prepare an epitaxial wafer. Thirdly, the temperature is reduced to 900 DEG C from 1130 DEG C; and depositing a thin film layer on the surface of the epitaxial layer of the epitaxial wafer by using a physical vapor deposition method. And 4, removing the thin film layer and the local epitaxial layer on the surface of the epitaxial wafer by using