Error identification method and device of chip system, chip and traffic equipment

The invention provides an error recognition method and device for a chip system, a chip and traffic equipment. The method comprises the steps that a first processor in the chip system obtains a first instruction sequence; generating a second instruction sequence in response to the fact that the lock step identification bit for the first instruction sequence is valid; instructions in the second instruction sequence are completely the same as instructions in the first instruction sequence; adding a first identifier for identifying the first instruction sequence and a second identifier for identifying the second instruction sequence; the first identifier is different from the second identifier; executing instructions in the first instruction sequence to obtain a first execution result, and storing the first execution result and the first identifier; executing instructions in the second instruction sequence to obtain a second execution result, and storing the second execution result and the second identifier; and