Chip surface defect detection method of compressed multi-head self-attention neural network
The invention belongs to the field of defect detection and image processing, and relates to a chip surface defect detection method based on a compressed multi-head self-attention neural network, which comprises the following steps of: photographing and collecting images on the surface of a chip by u...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention belongs to the field of defect detection and image processing, and relates to a chip surface defect detection method based on a compressed multi-head self-attention neural network, which comprises the following steps of: photographing and collecting images on the surface of a chip by using visible light imaging equipment, marking normal chips and defect chips in each image, and constructing a target detection data set; constructing a convolutional neural network initial model; training the initial model; and inputting a test set image in the constructed data set into a final model of the convolutional neural network based on the compressed multi-head self-attention mechanism to complete chip surface defect detection. According to the invention, the technical problems of poor detection effect and low calculation efficiency of small-size and high-density defect targets in a chip surface image when a chip with surface defects is detected in the prior art are solved.
本发明属于缺陷检测以及图像处理领域,一种压缩多头自注意力神经网络 |
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