Verification method for improving verification efficiency of complex chip system

The invention discloses a verification method for improving verification efficiency of a complex chip system. The verification method comprises the following steps: storing common problems which are summarized into a state register; the assertion module is triggered by the state register module, and the assertion module controls the unloading register module, so that the unloading register module unloads data when the system runs mistakenly; when the unloading is carried out, the assertion module locks the dynamically changing data in all the registers until the unloading is finished; outputting all the transferred data, and classifying according to the hierarchy of time, problem, module and register; and a new problem and a verification method are summarized. According to the invention, the efficiency of finding and solving problems by verification personnel is improved, the completeness of verification work is further improved, the chip success probability is improved, the cost and time are saved, and the v