CMOS device manufacturing method based on multilayer stress memory technology

The invention provides a CMOS (Complementary Metal Oxide Semiconductor) device manufacturing method based on a multilayer stress memory technology, which comprises the following steps of: depositing an etching barrier layer on a wafer, and carrying out plasma nitriding treatment on the etching barrier layer; depositing a high tensile stress layer on the processed etching barrier layer for n times, and carrying out plasma nitriding treatment on the high tensile stress layer; depositing a low-tensile-stress layer on the uppermost high-tensile-stress layer subjected to plasma nitriding treatment; wherein the tensile stress and the hydrogen content of the low-tensile-stress layer are both smaller than those of the high-tensile-stress layer; performing rapid thermal annealing on the wafer on which the etching barrier layer, the high tensile stress layer and the low tensile stress layer are deposited; and etching the wafer after rapid thermal annealing, and removing all the stress layers. By using the semiconductor