Serializer/deserializer (SERDES) channels with channel-by-channel data rate independence

The invention relates to a serializer/deserializer (SERDES) channel with channel-by-channel data rate independence. A circuit and method enable multiple serializer/deserializer (SerDes) data channels of a physical layer device (PHY) to operate across a wide variety of data rates that are independent from one channel to another. The plurality of SerDes data channels may operate at data rates that are independent of each other. A single low frequency clock is input to the PHY. The frequency of a single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each SerDes data channel operates independently as a fractional-N PLL employing the clock of the higher frequency. The use of a common integer N-PLL enables suppression of the modulation noise of a fractional-N PLL by shifting the modulation noise to a higher frequency in which the level of modulation noise is filtered, thereby avoiding the use of a high risk noise cancellation technique