Clock and data recovery circuit and signal processing method thereof

The invention provides a CDR circuit and a signal processing method thereof. The CDR circuit comprises a phase detector, a neural network circuit, a controller and a clock signal generator. The phase detector is configured to sample an input signal using a clock signal to produce a plurality of phase detection results. The neural network circuit is coupled to the phase detector for receiving a plurality of phase detection results to determine frequency difference information between the clock signal and the input signal. The controller is used for generating a control signal according to frequency difference information of a clock signal and an input signal. The clock signal generator is configured to adjust a phase or frequency of the clock signal output to the phase detector using the control signal. According to the CDR circuit, even if the input signal has large jitter, the phase of the input signal can be well locked all the time. 本发明提供了一种CDR电路及其信号处理方法，CDR电路包括相位检测器、神经网络电路、控制器和时钟信号产生器。相位检测器被配置为使用时钟信号对输入信号